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TDA7266D
5W+5W DUAL BRIDGE AMPLIFIER
PRELIMINARY DATA
s s
WIDE SUPPLY VOLTAGE RANGE (3.5 - 12V) OUTPUT POWER 5+5W @THD = 10%, R L = 8, VCC = 9.5V SINGLE SUPPLY MINIMUM EXTERNAL COMPONENTS - NO SVR CAPACITOR - NO BOOTSTRAP - NO BOUCHEROT CELLS - INTERNALLY FIXED GAIN
TECHNOLOGY BI20II
s s
s s s
STAND-BY & MUTE FUNCTIONS SHORT CIRCUIT PROTECTION THERMAL OVERLOAD PROTECTION
PowerSO20 Slug Down ORDERING NUMBER: TDA7266D
DESCRIPTION The TDA7266D is a dual bridge amplifier specially TEST AND APPLICATION CIRCUIT
designed for LCD TV/Monitor, PC Motherboard, TV and Portable Audio applications.
VCC JP1 R1 47K R2 47K IN1 S-GND R3 10K 9 C4 10F Vref C5 0.22F IN2 MUTE R4 10K 8 C6 1F 1 10 11 PW-GND 20 +
D02AU1407
+5V
C3 0.22F
6 7 + 13
15 2
C1 470F OUT1+
C2 100nF
C7 100nF
ST-BY
+ + -
5
OUT1-
14
19
OUT2+
16
OUT2-
May 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS
Symbol Vs IO Ptot Top Tstg, Tj Supply Voltage Output Peak Current (internally limited) Total Power Dissipation (Tamb = 70C Operating Temperature Storage and Junction Temperature Parameter Value 20 1.5 25 0 to 70 -40 to 150 Unit V A W C C
THERMAL DATA
Symbol Rth j-case Rth j-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient (on recomended PCB) note1 Value 2.1 15 Unit C/W C/W
Notes: 1. See Application note AN668, available on WEB FR4 with 15 via holes and ground layer.
PIN CONNECTION
PW GND OUT1+ N.C. N.C. OUT1VCC IN1 MUTE ST BY PW GND
1 2 3 4 5 6 7 8 9 10
D02AU1408
20 19 18 17 16 15 14 13 12 11
PW GND OUT2+ N.C. N.C. OUT2VCC IN2SGND N.C. PW GND
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ELECTRICAL CHARACTERISTCS (Refer to test circuit) VCC = 9.5V, RL = 8, f = 1KHz, Tamb = 25C unless otherwise specified)
Symbol VCC Iq VOS PO THD Parameter Supply Range Total Quiescent Current Output Offset Voltage Output Power Total Harmonic Distortion THD 10% PO = 1W PO = 0.1W to 2W f = 100Hz to 15KHz SVR CT AMUTE Tw GV GV Ri VTMUTE Supply Voltage Rejection Crosstalk Mute Attenuation Thermal Threshold Closed Loop Voltage Gain Voltage Gain Matching Input Resistance Mute Threshold for VCC > 6.4V; Vo = -30dB for VCC < 6.4V; Vo = -30dB VTST-BY IST-BY eN St-by Threshold St-by Current V6 = GND Total Output Voltage A Curve 150 25 2.3 VCC/2 -1 0.8 30 2.9 VCC/2 -0.75 1.3 4.1 VCC/2 -0.5 1.8 100 25 f = 100Hz, VR =0.5V 40 46 60 56 60 80 150 26 27 0.5 4.3 5 0.05 0.2 1 Test Condition Min. 3.5 Typ. 9.5 50 Max. 12 60 120 Unit V mA mV W % % dB dB dB C dB dB K V V V A V
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APPLICATIVE SUGGESTIONS STAND-BY AND MUTE FUNCTIONS (A) Microprocessor Application In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right Stby and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 1 and 2). At first St-by signal (from P) goes high and the voltage across the St-by terminal (Pin 9) starts to increase exponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to avoid "POP" and "CLICK" on the outputs. When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in series to the input terminals (C1, C3) start to charge. It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device goes in play mode causing a loud "Pop Noise" on the speakers. A delay of 100-200ms between St-by and mute signals is suitable for a proper operation. Figure 1. Microprocessor Application
VCC C1 0.22F IN1 ST-BY R1 10K C2 10F C5 470F OUT1+ C6 100nF
7
6 + -
15 2
9
P
S-GND
13 Vref + + 8 19 OUT2+ 5 OUT1-
C3 0.22F IN2 MUTE R2 10K C4 1F
14
1 10 11 PW-GND 20 +
D02AU1409
16
OUT2-
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TDA7266D
Figure 2. Microprocessor Driving Signals
+VS(V) +18
VIN (mV)
VST-BY pin 9 1.8 1.3 0.8 VMUTE pin 8 4.1 2.9 2.3
Iq (mA)
VOUT (V) OFF ST-BY PLAY MUTE MUTE ST-BY OFF
D02AU1411
B) Low Cost Application In low cost applications where the mP is not present, the suggested circuit is shown in fig.3. The St-by and mute terminals are tied together and they are connected to the supply line via an external voltage divider. The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by and mute threshold exceeding, avoiding "Popping" problems. So to avoid any popping or clicking sond, it is important to clock: a Correct Sequence: At turn-ON, the Stand-by must be removed at first, then the Mute must be released after a delay of about 100-200ms. On the contrary at turn-OFF the Mute must be activated as first and then the Stand-by. With the values suggested in the Application circuit the right operation is guaranteed. b Correct Threshold Voltages: In order to avoid that due to the spread in the internal thresholds (see the above limits) a wrong external voltage causes uncertain commutations for the two functions we suggest to use the following values: Mute for Vcc>6.4V Mute for Vcc<6.4V Stand-by : VT = 2.3V : VT = Vcc/2 - 1 : VT = 0.8V
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TDA7266D
Figure 3. Stand-alone low-cost Application
VCC C1 470F OUT1+ C2 100nF C7 100nF
C3 0.22F R1 47K IN1 ST-BY R2 47K C4 10F
7
6 + -
15 2
9
S-GND
13 Vref + + 19 OUT2+ 5 OUT1-
C5 0.22F IN2
14
MUTE
8
1 10 11 PW-GND 20 +
D02AU1410
16
OUT2-
PCB Layout and External Components: Regarding the PCB layout care must be taken for three main subjects: c) Signal and Power Gnd separation d) Dissipating Copper Area e) Filter Capacitors positioning )Signal and Power Gnd separation: c To the Signal GND must be referred the Audio Input Signals, the Mute and Stand-by Voltages and the device PIN.13. This Gnd path must be as clean as possible in order to improve the device THD+Noise and to avoid spurious oscillations across the speakers. The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed by large amount of current, this path is also used in this device to dissipate the heating generated (no needs of external heatsinker). Referring to the typical application circuit, the separation between the two GND paths must be obtained connecting them separately (star routing) to the bulk Electrolithic capacitor C1 (470F). Regarding the Power Gnd dimensioning we have to consider the Dissipated Power the Thermal Protection Threshold and the Package thermal Characteristics.
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d Dissipating Copper Area: Dissipated Power: The max dissipated power happens for a THD near 1% and is given by the formula:
V CC P dmax ( W ) = 2 ------------- + I q V CC 2 Rl ----2
2
This gives for: Vcc = 9.5V, Rl = 8 ,Iq = 50mA a dissipated power of Pd = 5W. Thermal Protection: The thermal protection threshold is placed at a junction temperature of 150C.
Package Thermal Characteristics: The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via holes (see picture) is about 15C/W. This means that with the above mentioned max dissipated Power (Pd=5W) we can expect a 75C, this gives a safety margin before the thermal protection intervention in the consumer environments where a 50C ambient is specified as maximum
The Thermal constraints determine the max supply voltage that can be used for the different Load Impedances, this in order to avoid the thermal Protection Intervention. The max. dissipated power must be not in excess of 5W , this at turns gives the following operating supply voltages:
Load (Ohm) 4 6 8 16 Supply Voltage (V) 6.5 8.5 9.5 14
e Filter Capacitors Positioning: The two Ceramic capacitors C2/C7 (100nF) must be placed as close as possible respectively to the two Vcc pins ( 6 - 15) in order to avoid the possibiltiy of oscillations arising on the output Audio signals. Package Informations: You can find a complete description for the PowerSO package into the APPLICATION NOTE AN668 available on web. Here we want to focalize the attention only on the the Dissipating elements and ground layer.
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Considering the dissipated power involved in the TDA7266D application that is in the range of 5W, as explained in a previous section, we suggest via holes ( see fig. 4). Using via holes a more direct thermal path is obtained from the slug to the ground layer.The number of vias is chosen accordingly to the desired performance (in our demonstration board we use 15 vias). In fig.4 is shown as an example the footprint to be used to create the vias. Figure 4.
The above metioned mounting solution is enough to dissipate the power involved In the most part of the application using the TDA7266D. If necessary a further improvement in the Rth J-Ambient can be obtained as shown in fig.5 where the PowerSO20 is soldered onto a via hole structure with a metal plate glued on the opposite side of the board. Figure 5. Mounting on epoxy FR4 using via Holes for heat transfer and external metal plate
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TDA7266D
Figure 6. Distortion vs Frequency
THD(%)
10
Figure 9. Stand-By attenuation vs Vpin 9
Attenuation (dB)
1
Vcc = 9.5 V Rl = 8 ohm
0.1
Pout = 100mW
Pout = 2W 0.010 100 1k 10k 20k
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4
frequency (Hz)
Vpin.7 (V)
Figure 7. Gain vs Frequency
Level(dBr)
5.0000 4.0000 3.0000 2.0000 1.0000 0.0 -1.000 -2.000 -3.000 -4.000 -5.000 10 100 1k 10k 100k Vcc = 9.5V Rl = 8 ohm Pout = 1W
Figure 10. Quiescent Current vs Supply Voltage
Iq (mA)
70 65 60 55 50 45 40 35 30 3 4 5 6 7 8 9 10 11 12
frequency (Hz)
Vsupply(V)
Figure 8. Mute Attenuation vs Vpin.8
Attenuation (dB)
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 1.5 2 2.5 3 3.5 4 4.5 5
Figure 11. Total Power Dissipation & Efficiency vs Pout
Pd(W) 6
70 Eff(%)
5
60
4
Vcc= 9.5V Rl = 8 ohm f=1KHZ 2 Channels
50
3
40
2
30
1
20
Vpin.6(V)
0 0 1 2
2 X Pout (W)
10 3 4 5
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TDA7266D
Figure 12. THD+N vs Output Power
10 THD(%) 5 2 1 0.5 0.2 0.1
Vcc=9.5V Rl=8ohm f=1KHz
Figure 13. THD+N vs Output Power
THD(%) 10 5 2 1 0.5 0.2 0.1 0.05 0.02
Vcc=12V Rl=16 ohm f = 1KHz
100m
200m 300m 500m700m 1 Pout(W)
2
3
4 56
0.01 100m
200m 300m
500m 700m
1
2
3
45
Pout(W)
Figure 14. PC Board Component Layout
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TDA7266D
Figure 15. Evaluation Board Top Layer Layout
Figure 16. Evaluation Board Bottom Layer Layout
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TDA7266D
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T
mm MIN. 0.1 0 0.4 0.23 15.8 9.4 13.9 1.27 11.43 10.9 5.8 0 15.5 0.8 11.1 2.9 6.2 0.1 15.9 1.1 1.1 0.031 8 (typ.) 8 (max.) 10 0.228 0.000 0.610 0.429 TYP. MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.004 MIN.
inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166
Weight: 1.9gr
OUTLINE AND MECHANICAL DATA
0.394
(1) "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions: "E", "G" and "a3".
PowerSO20
N
N a2 b e A
R
c DETAIL B a1 E DETAIL A
DETAIL A e3 H
lead
D a3 DETAIL B
20 11
Gage Plane 0.35
slug
-C-
S E2 T E1 BOTTOM VIEW
L
SEATING PLANE G C
(COPLANARITY)
E3
1 10
h x 45
PSO20MEC
D1
0056635
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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